• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Artikel
  4. Silver Sintering of Packaged GaN-Devices on Printed Circuit Board
 
  • Details
  • Full
Options
2022
Journal Article
Title

Silver Sintering of Packaged GaN-Devices on Printed Circuit Board

Abstract
Despite the higher thermal conductivity and the higher lifetime offered by silver sintering technologies, most packaged GaN devices are attached using solders due to technological difficulties in the sintering process. In this work, a silver sintering process for a packaged GaN power transistor on a printed circuit board (PCB) was successfully developed. Different sintering paste types were examined regarding their suitability for this application. Electrical measurements, shear tests, and metallographic cross sections were used for the evaluation. Numerical analyses were used to study the internal stress distribution in the GaN package after sintering depending on the paste structure. In the final sintering process, a shear strength of 20 MPa for sintering at 15 MPa and 240°C, for 300 s with electrical functional devices could be obtained by using nanoscale sintering paste. The authors contribute this to the high initial stiffness of the silver layer, which is obtained much earlier in the sintering process compared with the stiffness of a microscale silver paste. This high initial stiffness counteracts the semiconductor device deflection from the applied sintering pressure and reduces the stresses inside the semiconductor.
Author(s)
Müller, Jonas
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Letz, Sebastian A.  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Flaviu-Bogdan, Simon
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Bayer, Christoph F.  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Schletz, Andreas  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Görlich, Jens
Nishimura, Takatoshi
Journal
Journal of microelectronics and electronic packaging  
Open Access
DOI
10.4071/imaps.1675410
Language
English
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Keyword(s)
  • FEM

  • GaN package

  • HEMT

  • die bonding

  • nanoscale sintering paste

  • Numerical analysis

  • power electronics packaging

  • printed circuit board

  • silver sintering

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024