Design of a Highly Efficient Buck Converter in 22nm FDSOI Technology

The master thesis `Development of a Highly Efficient DC-DC Converter using 22nm FDSOI Technology' involves two major parts. These are the digital control loop and the power train circuit. The digital control loop has been modelled using System Verilog and the power train circuit is designed using the components from the PDK 22nm FDSOI. This DC-DC converter is developed using a voltagecontrolled loop. It involves the technique of pulse width modulation which is modelled using digital pulse width modulated (DPWM) signals' generator using delay line based architecture. The DC-DC converter used in this thesis is a flying capacitor multi-level (FCML) converter. The goal of the thesis is to achieve 1.8V and 0.8 V at output with less than 50 mV voltage ripples for an input of 4V, with high efficiency. The losses due to switches were reduced, however, an on-chip inductor dissipated approximately 14% of the input power, therefore, an on-chip inductor is suggested. In this thesis, maximum efficiency achieved withan on-chip inductor is 71.9% at an output current of 306 mA, whereas 85.7% efficiency is achieved for an off-chip inductor at an output current of approximately 590 mA for 1.8 V. The maximum efficiency achieved for 0.8 V with an on-chip inductor is 70.6% at an output current of 197 mA, whereas 88.5% efficiency is achieved for an off-chip inductor at an output current of approximately 406 mA. By natural balancing of the flyying capacitors of a hybrid (FCML) DC-DC converter,the output of the DC-DC converter is successfully achieved. It also involves the stability analysis of the DC-DC converter.