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  4. Special session: Physical attacks through the chip backside: Threats, challenges, and opportunities
 
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2021
Conference Paper
Title

Special session: Physical attacks through the chip backside: Threats, challenges, and opportunities

Abstract
This paper reviews the evolution of a powerful class of physical attacks against integrated circuits (ICs), developed initially for performing failure analysis (FA) from the IC backside. Over the last two decades, several publications have demonstrated the effectiveness of these techniques in bypassing the IC protection schemes and extracting the stored assets inside secure ICs. In this work, we take a fresh look at such hardware attacks from three different perspectives. First, we will discuss the potential threat of the attacks against modern technologies and demystify a set of wrong beliefs about the attacks' complexity. Second, we review some technical challenges of such attacks from a law enforcement agency's perspective for unraveling crimes and preventing further crimes by criminals involved. Finally, we give an insight into the future development of FA tools and the opportunities for designing effective countermeasures against attacks through the chip backside.
Author(s)
Amini, E.
Bartels, K.
Boit, C.
Eggert, M.
Herfurth, N.
Kiyan, T.
Krachenfels, T.
Seifert, J.-P.
Tajik, S.
Mainwork
IEEE 39th VLSI Test Symposium, VTS 2021. Proceedings  
Conference
VLSI Test Symposium (VTS) 2021  
DOI
10.1109/VTS50974.2021.9441006
Language
English
Fraunhofer-Institut für Sichere Informationstechnologie SIT  
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