Investigation of GaN-on-Si and GaN-on-SOI substrate capacitances for discrete and monolithic half-bridges
While the lateral GaN power integration technology allows integration of half-bridges, the conductive Si-substrate causes static and dynamic biasing effects. This work investigates capacitance-related effects in monolithic half-bridges on GaN-on-Si and GaN-on-SOI substrates and various feasible substrate terminations. The effect of the substrate capacitances and termination on the effective CISS, COSS, CRSS device capacitances and switch-node capacitance CSW, switching energy ESW and gate-charge QG in half-bridges is analyzed. A gate-to-gate crosscoupling capacitance CXSS in monolithic GaN-on-Si half-bridges on floating substrates is revealed. Furthermore, a small unintentional integrated dc-link capacitance CDC also follows from the analysis for monolithic GaN-on-Si half-bridges on floating substrate. Measurements of GaN-on-Si half-bridges with different substrate terminations verify the analysis. The analysis of the GaN-on-Si half-bridge with floating substrate shows an effectively reduced output capacitance and the best trade-off in terms of CRSS increase, which is verified by measurements where it shows the highest hard-switching dc-dc efficiency of the analyzed configurations. The analysis shows how buried oxides in GaN-on-SOI half-bridges increases switch-node capacitance and thus switching losses or times. At 200V, the efficiency of the GaN-on-Si half-bridge on floating substrate, as feasible for a monolithic half-bridge, exceeds the measured efficiency of a conventional half-bridge due to the reduced effective capacitance.