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2020
Conference Paper
Title
Design and fabrication of 4h-Sic Mosfets with optimized JFET and p-body design
Abstract
In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide's critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO2 and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm-2eV-1 at EC - EIT = 0.21 eV and channel mobility of 19.3 cm2/Vs at VGS = 20 V were obtained. The fabricated MOSFET's on-resistance of 6.4 mOcm2 was obtained with hexagonal cell structure which is very consistent with the simulation results.
Author(s)
Ni, W.
Key Lab of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
Wang, X.
Key Lab of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
Feng, C.
Key Lab of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
Xiao, H.
Key Lab of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
Jiang, L.
Key Lab of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
Li, W.
Key Lab of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
Wang, Q.
Key Lab of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China