Degradation modeling and validation - bottlenecks for standard use of aging simulations in IC design

Qualification according to the industry-standard AEC-Q100 is state of the art to verify the reliability of integrated circuits that are applied in automotive electronics. However, there are indications that this will not be sufficient for future applications. Instead, simulation-based reliability assessments in IC and system development are intended to complement qualification and allow efficient investigations of product reliability. Aging simulations for analog circuits have been available for years but appear to be hardly used. This article outlines degradation models and validation as bottlenecks that have to be overcome to establish aging simulations as a standard verification step in the future.