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2020
Conference Paper
Title

XMSS and Embedded Systems

Title Supplement
XMSS Hardware Accelerators for RISC-V
Abstract
We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We provide software optimizations for the XMSS reference implementation for SHA-256 parameter sets and several hardware accelerators that allow to balance area usage and performance based on individual needs. By integrating our hardware accelerators into the RISC-V processor, the version with the best time-area product generates a key pair (that can be used to generate 210 signatures) in 3.44 s, achieving an over 54× speedup in wall-clock time compared to the pure software version. For such a key pair, signature generation takes less than 10 ms and verification takes less than 6 ms, bringing speedups of over 42× and 17× respectively. We tested and measured the cycle count of our implementation on an Intel Cyclone V SoC FPGA. The integration of our XMSS accelerators into an embedded RISC-V processor shows that it is possible to use hash-based post-quantum signatures for a large variety of embedded applications.
Author(s)
Wang, Wen
Yale University, New Haven, CT, USA
Jungk, Bernhard
Independent Researcher
Wälde, Julian  
Fraunhofer-Institut für Sichere Informationstechnologie SIT  
Deng, Shuwen
Yale University, New Haven, CT, USA
Gupta, Naina
Fraunhofer Singapore  
Szefer, Jakub
Yale University, New Haven, CT, USA
Niederhagen, Ruben
Fraunhofer-Institut für Sichere Informationstechnologie SIT  
Mainwork
Selected Areas in Cryptography - SAC 2019  
Funder
National Science Foundation NSF  
Conference
International Conference on Selected Areas in Cryptography (SAC) 2019  
DOI
10.1007/978-3-030-38471-5_21
Language
English
Singapore  
Fraunhofer-Institut für Sichere Informationstechnologie SIT  
Keyword(s)
  • XMSS

  • hash-based signatures

  • post-quantum cryptography

  • hardware accelerator

  • FPGA

  • RISC-V

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