Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits

In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxial layer in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mOcm2 for a device with a RESURF structure (REduced SURface Field) with a total implanted Al concentration of 6∙1016 cm-3 and a depth of 1 mm, a field plate of 5 mm and a drift region of 20 mm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).