Fast Analog Layout Migration with IIP-based Automation

Analog integrated circuits are to the largest part still designed manually. Tools for sizing already support both design porting and sizing significantly. In order to increase efficiency also in the layout phase, Fraunhofer IIS/EAS works on layout generators. Such generators are used as add-on automation tools in the standard analog design flow. This way, layout is estimated faster, design is accelerated and reuse of IP across technologies is eased. Particular accelerated design examples are presented, insight into the EDA methods is given, and an outlook to closer coupling of automated sizing and generator-based automation is presented.