SiC power module loss reduction by PWM gate drive patterns and impedance-optimized gate drive voltages

This paper presents a novel procedure to determine the internal gate-source voltage inside a multi-chip power module using the example of a SiC half bridge module. Based on the lumped elements of the gate circuit calculated by a quasi-static electromagnetic simulation, each field-effect transistor is represented by a single, voltage dependent capacitor. The procedure is validated by clamped inductive switching measurements of a SiC power module. Moreover, it is applied to determine the maximum permissible gate-source voltage range in compliance with the manufacturer's voltage rating for a given driver-module combination. In this context a significant extension of the gate drive voltage range and thus an increase of efficiency using impedance specific PWM patterns is demonstrated.