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  4. Process variability for devices at and beyond the 7 nm node
 
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2018
Conference Paper
Title

Process variability for devices at and beyond the 7 nm node

Abstract
Advanced CMOS devices are increasingly affected by various kinds of process variations. Whereas the impact of statistical process variations such as Random Dopant Fluctuations has for several years been discussed in numerous publications, the effect of systematic process variations which result from non-idealities of the equipment used or from various layout issues has got much less attention. Therefore, in the first part of this paper, an overview of the sources of process variability is given. In order to assess and minimize the impact of variations on device and circuit performance, relevant systematic and statistical variations must be simulated in parallel, from equipment through process to device and circuit level. Correlations must be traced from their source to the final result. In this paper the approach implemented in the cooperative European project SUPERAID7 to reach these goals is presented.
Author(s)
Lorenz, Jürgen  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Asenov, Asen
Glasgow University
Bär, Eberhard  orcid-logo
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Barraud, Sylvain
CEA-Leti
Millar, Campbell
Synopsys
Nedjalkov, Mihail
TU Wien
Mainwork
Advanced CMOS-Compatible Semiconductor Devices 18  
Project(s)
SUPERAID7  
Funder
European Commission EC  
Conference
Symposium "Advanced CMOS-Compatible Semiconductor Devices" 2018  
Electrochemical Society (ECS Meeting) 2018  
File(s)
Download (990.36 KB)
Rights
Under Copyright
DOI
10.24406/publica-r-400444
10.1149/08508.0113ecst
Language
English
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Keyword(s)
  • process variation

  • process simulation

  • device simulation

  • interconnect simulation

  • compact model

  • hierarchical simulation

  • nanowire transistor

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