Optimum gate driver design to reach SiC-MOSFET's full potential - speeding up to 200 kV/µs

Low conduction losses are one technical advantage of SiC-MOSFETs compared to conventional IGBTs but this benefit is generally not enough to justify the much higher wafer costs per mm2. The other very important advantage is the lower switching losses. A conventional power module design with externally connected gate drivers cannot even get into the region of what SiC-MOSFETs are capable to perform. One reason are high parasitic inductances caused by the module design (gate and drain-source inductance) but another reason is the very sensitive gate structure of today's SiC-MOSFETs compared to Si-switches. This abstract reveals the requirements a driver has to fulfil to switch SiC-MOSFETs at their maximum switching speed and shows how it is done in practical applications. Differences in the gate behavior of SiC-MOSFETs and Si-competitors are illustrated. Practical solutions are depicted and evaluated for different applications.