Simplifying UVM in SystemC

UVM-SystemC is currently under standardization within Accellera with a first preview release expected in 2015. Although, the UVM standard is getting more and more language-agnostic with implementations available in e, SystemVerilog, and now SystemC, features for transaction-based stimulus and verification environment modeling still strongly rely on the underlying language. For example, packing, copying, and randomization operations are implemented differently in each of these languages; certain features such as aspect-oriented extensions of classes and methods are currently only available in e.