Investigation of chip-to-chip interconnection structures for high data rates on a low cost silicon interposer

Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip via an interposer. We use a typical silicon interposer with polymer applied to the redistribution layer on both sides and line/space of 10 µm. We point out important advantages and differences of the chip-to-chip interconnection in comparison to usual integration using a separate package for each chip and a printed circuit board. The electrical behavior of the interconnections is simulated. The results demonstrate a 2 Gbps communication on a 9 mm long interposer interconnection. The average power consumption of a state transition of the chip-to-chip interconnection is simulated and compared to the power consumption of a typical PCB transmission line. The results show that the interposer interconnection consumes significantly more power per length than a typical PCB trace because of his increased resistance. Because of that we recommend to not decrease the line/space beyond 10 µm for chip-to-chip interconnections.