Market drivers and architectural requirements for backplane inter-connect capacities in next generation PON head-end equipment in the access network

This paper examines the market drivers and architectural requirements for the evolution of Access Network PON 'Head-End' equipment in the FP7 PIANO+ timescales and the implications for the internal backplane interconnect capacities within such equipment. It then outlines the solutions proposed within the SEPIANet project to achieve these capacities and gives an interim view of the project achievements.