Electrical impact of the aluminum p-implant annealing on lateral MOSFET transistors on 4H-SiC n-epi

In this work we investigate the effect of the aluminum p-well implant annealing process on the electrical properties of lateral 4H-SiC MOSFET transistors. The interface trap concentration was measured by quasi-static capacitive voltage (QSCV) and negative bias stress measurements on MOSFETs. We found that higher annealing temperatures significantly reduce the trap density in the lower bandgap, and as a consequence the threshold voltage drift of the transistor after negative stress is reduced.