Utilizing coupled process and device simulation for optimization of sub-quarter-micron CMOS technology

Coupled process and device simulation was applied for the optimization of sub-quarter-micron CMOS technology. Optimum conditions for critical ion implantation steps were found. Especially it was shown that an increased implantation dose of the source and drain extensions improves the device performance. On this basis, the device performance achievable when shrinking to the $0.15 mu m$ generation of CMOS technology was estimated. Finally, an example of the coupled three-dimensional process and device simulation which indicates the role of 3D effects in small size CMOS transistors is presented.