On-chip focal plane filtering for CMOS imagers

The use of the CMOS technology for imaging enables the cointegration of additional signal processing circuitry on the same chip as the imager. We propose an architecture for a CMOS imager with linear voltage readout and on-chip filtering. Instead of increasing the pixel complexity, we have realized the filtering at the periphery of the imager. Therefore, the pixel pitch can be preserved without degrading the fill factor and requiring large optics.