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  4. Realization and evaluation of an ultra low-voltage/low-power 0.25 mu m (n+/p+) dual-workfunction CMOS technology
 
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1997
Conference Paper
Title

Realization and evaluation of an ultra low-voltage/low-power 0.25 mu m (n+/p+) dual-workfunction CMOS technology

Other Title
Realisierung und Evaluierung einer Niedervolt/Energiespar 0.25 mu m (n+/p+) Dual-Gate-CMOS-Technologie
Abstract
The ultimate goal for low power applications is aimed at single-battery operation with a nominal supply voltage of 1.2V and an end-of-life voltage of 0.9V. In this work results on process optimization, device characterization, dynamic performance and hot carrier degradation of an ultra low-power/low-voltage (1.2V) quarter-micron dual-workfunction CMOS technology with low process complexity are presented.
Author(s)
Schwalke, U.
Berthold, J.
Burenkov, A.  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Eisele, M.
Krieg, R.
Narr, A.
Schumann, D.
Seibert, R.
Thanner, R.
Mainwork
ESSDERC '97. Proceedings of the 27th European Solid-State Device Research Conference  
Conference
European Solid-State Device Research Conference (ESSDERC) 1997  
Language
English
IIS-B  
Keyword(s)
  • Bauelemente-Simulation

  • CMOS-Technologie

  • CMOS technology

  • device simulation

  • Dual-Gate-Technologie

  • dual-gate technology

  • dünne Gateoxide

  • Energiesparelektronik

  • Low-Power

  • low voltage

  • process simulation

  • Prozeßsimulation

  • thin gate oxides

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