• English
  • Deutsch
  • Log In
    or
  • Research Outputs
  • Projects
  • Researchers
  • Institutes
  • Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Konferenzschrift
  4. Chipset for a single-board MPEG-2 SSP@H-1440L HDTV-decoder
 
  • Details
  • Full
Options
1995
Conference Paper
Titel

Chipset for a single-board MPEG-2 SSP@H-1440L HDTV-decoder

Abstract
This paper presents the VLSI realization of an MPEG-2 conformant hierarchical video decoder based on the spatially scalable profile at the High-1440 Level (SSP@H-14L). The decoder is built at the Heinrich-Hertz-Institut (HHI) as part of the ongoing joint R&D project "Hierarchical digital television transmission" (HDTVT) and will be demonstrated during the international exhibition IFA 1995 in Berlin. The project proposes a compatible approach to HDTV (TV-HDTV compatibility due to spatial scalability). Terrestrial broadcasting with graceful degradation and portable reception (through spatial and SNR scalability) are supported besides the less demanding cable and satellite scenarios. Two chips are currently under development to achieve an integrated hardware solution for the hierarchical MPEG-2 video source decoder. The first chip, BISTRO, incorporates all functions from transport stream reception up to the IDCT. The second chip, MOFA, is performs upconversion, motion compensation, global frame store addressing and digital output of the decoded data. The design concept uses logic synthesis from VHDL. The design is verified through automatic comparison with the results from a high-level MPEG-2 reference program. An on-board DSP supports board self-test and serves for system monitoring during field trials. The complete hierarchical HDTV video decoder fits on one single PCB.
Author(s)
Selinger, T.
Block, M.
Kanold, P.
Talmi, M.
Yan, W.
Zhang, W.
Zieger, M.
Hauptwerk
Signal processing of HDTV, VI
Konferenz
International Workshop on HDTV 1994
Thumbnail Image
Language
English
google-scholar
Fraunhofer-Institut für Nachrichtentechnik, Heinrich-Hertz-Institut HHI
Tags
  • cable television

  • digital signal proces...

  • digital television

  • direct broadcasting b...

  • hardware description ...

  • high definition telev...

  • motion compensation

  • source coding

  • television broadcasti...

  • television reception

  • video equipment

  • video signal processi...

  • vlsi

  • chipset

  • single-board mpeg-2 H...

  • vlsi realization

  • mpeg-2 conformant hie...

  • high-1440 level

  • heinrich-hertz-instit...

  • hierarchical digital ...

  • HDTVt

  • tv-HDTV compatibility...

  • spatial scalability

  • terrestrial broadcast...

  • logic synthesis

  • vhdl

  • snr scalability

  • integrated hardware s...

  • bistro

  • transport stream rece...

  • idct

  • mofa

  • upconversion

  • global frame store ad...

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Send Feedback
© 2022