ESD monitor circuit. A tool to investigate the susceptibility and failure mechanisms of the charged device model

ESD-monitor circuits are introduced and used to evaluate failure mechanisms and susceptibilities with respect to the Charged Device Model. The performance of protection elements is studied by means of transmission line pulsing, electron beam probing and non-contact, non-socketed CDM-tests. The capacitance connected to the source of the protection transistor and the resistance of this connection are critical. With respect to the circuitry and protection element, CDM-failure signatures of the monitor vary from an energy induced junction failure to a voltage induced gate oxide breakdown.