Performance issues of SOI CMOS circuits at low supply voltages

The SPICE implementation of our previously presented charge sheet model of the SOI MOSFET has been used to investigate the performance of SOI CMOS circuits at typical battery voltages (1.35...1.55V). In comparison to conventional CMOS circuits, speed gains of more than 50 percent have been found, which is mainly due to the small parasitic capacitances and reduced short channel effects.