Paralleler AD-Umsetzer mit Schwellenwertspannungs-Einstellung

The first stage of a two-bit A/D convertor has three p-channel MOSFETs (M1(1)-M1(3)) with different dopant concentrations, each producing a digital output signal (e.g. Out(1)) for the next stage from the analogue input (U(in)). The n-channel MOSFETs (M2(1)-M2(3)) of the second stage acting as a 1-out-of-n encoder have pull-up resistances (R(PU)) and produce output voltages (A(1)-A(3)) for the third stage. This has two p-channel MOSFETs (M3(1),M3(2)) sharing a common pull-down resistance, and a third p-channel MOSFET (M3(3) with its own pull-down resistance (R(PD)). It has an output connection from each of the pull-down resistances. ADVANTAGE - A high power capability is achieved with a reduced requirement for chip area. 1a,1b,1c/5