SAR ADC Reference Buffer Design for Next-Gen Radar in 22 nm FD-SOI

Immense improvements in the field of wireless communications escalate the need for higher data rates and digitization of signals. To suffice this, high-speed and efficient Analog-to-Digital Converters are a need of the hour. Among them, Successive approximation ADCs with on-chip reference buffers have gained overwhelming attention for medium-to-high resolution data converters. Voltage reference buffers are the most-power-hungry band critical block of SAR ADCs. Dynamic loading of reference buffers creates a huge spike in the generated reference voltage. Prompt recovery and high accuracy of less than half the Least Significant Bit settling error are expected from the voltage buer. These rigorous requirements demand high performance and quick settling on-chip voltage buffers. This work aim s at designing a high-speed, fast settling reference buer for 10bit, 240 MS/s pipelined SAR ADC using 22 nm FD-SOI technology. Two different buer schemes are implemented with a DC gain of 63 dB. The three stage indirect compensated buer settles at 125.3 ps with an input-referred rms noise of 87.8 µV. Whereas, conventional folded cascode topology settles within 84.4 ps with an input noise level of 60.86 µV/rms. The layout of the folded cascode topology was done. Post-layout simulations were carried out and comparable results were achieved for Capacitor-only extraction.