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  4. Design of a 60 GHz 32% PAE Class-AB PA with 2nd Harmonic Control in 45-nm PD-SOI CMOS
 
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2020
Journal Article
Title

Design of a 60 GHz 32% PAE Class-AB PA with 2nd Harmonic Control in 45-nm PD-SOI CMOS

Abstract
This paper presents a 60 GHz highly efficient single stage differential stacked Class-AB power amplifier (PA) with second harmonic control (HC) for short range applications using mm-wave radar. The circuit is realized in a 45nm partially depleted sillicon-on-insulator (PD-SOI) CMOS technology. Measurement results show that the power amplifier achieves a saturated output power (Psat) of 16.4dBm with a competitive maximum power-added efficiency (PAEmax) of 32% at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a single 1.8V supply and the chip core size is 0.36mm × 0.35 mm.
Author(s)
Ciocoveanu, R.
Weigel, R.
Hagelauer, A.
Issakov, V.
Journal
IEEE transactions on circuits and systems. 1, Fundamental theory and applications  
DOI
10.1109/TCSI.2020.2984042
Language
English
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
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