Influence of Sacrificial Layer Germanium Content on Stacked-Nanowire FET Performance

The stacked nanowire field-effect transistor is an important option for future generations of CMOS technology. It features superior electrostatic control due to all-around gates while maintaining sufficient drive currents by stacking multiple channels. One of the challenges for manufacturing such devices is the fabrication of inner spacers between the nanowires in order to control the parasitic capacitances. A previously demonstrated approach for inner spacer fabrication uses the wet chemical etching of a sacrificial silicon-germanium layer between the silicon channels in order to prepare a cavity into which the spacer material is deposited. The etch rate of the sacrificial layer depends on the germanium content. Thus, the variations of the Si-Ge composition across the wafer lead to the corresponding geometrical variations of the transistor structures. This work traces the effect of Si-Ge composition variations via the inner spacer geometry on the key electrical properties of the devices using the numerical simulations. A significant impact on on-current and capacitances was determined. It could be shown that the dependence of the current on the Si-Ge composition is closely related to the doping profile in the nanowires. These results improve the understanding of sources of variability in nanowire transistors and, hence, may help to improve device reproducibility.