A Compact Model Based on Bardeens Transfer Hamiltonian Formalism for Silicon Single Electron Transistors

Presented is a physics-based compact model for a silicon-nanopillar single-electron transistor (SET). Tunneling currents are calculated using a master equation approach with rates obtained via the transfer Hamiltonian formalism. The quantum confinement of electrons on the quantum dot is taken into consideration by a suitable approximation as required for a nanometer-sized device. Device geometry and material properties enter the model directly as model parameters. Thus, this model enables the investigation of circuits and application scenarios for specific SET technologies in dependence on geometry and material variations. The model was implemented in HSPICE and used to simulate an inverter and a ring oscillator to evaluate the performance of the model. Specific device characteristics for a SET with a semiconducting quantum dot like the gate voltage threshold for the onset of current oscillations are reproduced. Therefore, simulations with the presented model will allow the testing of the SET circuits with more realistic assumptions concerning the device behavior compared to the much more abstract SET compact models available up to now.