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  4. Process variability - technological challenge and design issue for nanoscale devices
 
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2019
Journal Article
Title

Process variability - technological challenge and design issue for nanoscale devices

Abstract
Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.
Author(s)
Lorenz, Jürgen  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Bär, Eberhard  orcid-logo
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Barraud, Sylvain
CEA, LETI, MINATEC, Grenoble, France
Brown, Andrew R.
Synopsys Northern Europe Ltd., Glasgow, UK
Evanschitzky, Peter  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Klüpfel, Fabian
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Wang, Liping
Synopsys Northern Europe Ltd., Glasgow, UK
Journal
Micromachines  
Project(s)
SUPERAID7  
Funder
European Commission EC  
Open Access
DOI
10.3390/mi10010006
Additional full text version
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Language
English
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Keyword(s)
  • process simulation

  • device simulation

  • compact model

  • process variation

  • systematic variation

  • statistical variation

  • FinFET

  • nanowire

  • nanosheet

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