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  4. Optimized design for 4H-SiC power DMOSFETs
 
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2016
Journal Article
Title

Optimized design for 4H-SiC power DMOSFETs

Other Title
Optimiertes Design von 4H-SiC Leistungs-DMOSFETs
Abstract
An optimized tradeoff between blocking voltage and specific ON-resistance for 4H-silicon carbide power vertical double-implanted metal-oxide-semiconductor field-effect transistor (DMOSFET) is exclusively obtained as a function of doping concentration in the drift region. Based on a novel analytical model of the electric field in the gate oxide of 4H-SiC DMOSFETs, we propose a closed-form equation of the Junction FET (JFET) region width and the drift thickness as function of doping concentration without using fitting and empirical parameters to obtain the maximum figure of merit. Model results are successfully verified with TCAD numerical simulations, covering a wide range of device performances, and experimental results.
Author(s)
Benedetto, Luigi di
Univ. Salerno
Licciardo, Gian D.
Univ. Salerno
Erlbacher, Tobias  
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Bauer, Anton J.
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Rubino, Alfredo
Univ. Salerno
Journal
IEEE Electron Device Letters  
DOI
10.1109/LED.2016.2613821
Language
English
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB  
Keyword(s)
  • design methodology

  • Power MOSFET

  • semiconductor device modeling

  • silicon compound

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