Coupled simulation to determine the impact of across wafer variations in oxide PECVD on electrical and reliability parameters of through-silicon vias

We demonstrate a coupled equipment- and feature-scale process simulation and its application to plasma-enhanced chemical vapor deposition (PECVD) as part of a sequence for the fabrication of a through-silicon via (TSV) interconnect. The TSV structure is characterized electrically and mechanically by means of finite element simulation. This chain allows one to determine the effects of process variations on the electrical and reliability characteristics of the TSV. The simulations predict an across wafer variation of the parasitic DC capacitance between the tungsten metallization and the silicon substrate of about 3%. However, mechanical simulations indicate only a minor influence of the oxide layer thickness variation on the reliability performance of the TSV.