Application-driven simulation of nanoscaled CMOS transistors and circuits

Problems in the application-driven simulation of nanoscaled CMOS transistors and circuits are addressed in this paper. First, major physical effects determining the transistor performance at nanoscale gate lengths are considered, then a ver ification of the simulation models is shown. As example, a comparison of the sca ling properties of three MOS transistor architectures along the ITRS guide lines and a simulation of the dynamic performance of an SRAM circuit are considered. A newtypical feature of nanoscaled MOS transistors is that the transistor perfor mance is influenced by several additional physical effects and the effects which have been considered before as small, extrinsic, or parasitic are nowdeterminin g the transistor performance. At nanoscale, mechanical stress, contact resistanc es, and parasitic capacitances have important influences on MOS transistor perfo rmance. These parasitic factors determining the performance of the integrated ci rcuits based on nanoscaled transistors depend on the processing technology, devi ce architecture, and in certain cases also on circuit architecture.