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  4. Wafer level chip size package challenges
 
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2000
Journal Article
Title

Wafer level chip size package challenges

Abstract
The driving forces for new development in semiconductor IC technology are constant reductions in structure size and an increase in the overall electrical performance. The 0.25µm technology has been already introduced into high-volume production and is now heading for 0.18µm technology. A new area of chip production will start with the first wafer fabs doing CMOS on 300-mm (12-in.) wafers beginning 2000.
Author(s)
Töpper, M.
Reichl, H.
Journal
HDI magazine  
Language
English
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
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