Programmable signal processors

In many applications, the present 16-bit fixed decimal point arithmetic is insufficient. The processors of the next generation will use the floating decimal point representation of numbers and arithmetic. Of possible solutions, the single-chip processor is best suited to mass production and much preferred for real time operation. The existing processors use hardware multipliers, using the Booth algorithm; their calculating unit consists of a multiplier and an adder, working in parallel and pipeline formats. A floating decimal point processor, developed in the Heinrich Hertz Institute, is described. Its most distinctive feature is the complexity of calculations and addressings, and a new 'add and shift' multiplication. A design aid programme system for specific application has been also developed. The hardware simulation works faster than the software method.