Characterization of Pvd Backside Metal Adhesion for Improved Thermal Management in Heterogeneous Integration

Efficient heat dissipation in highly integrated and miniaturized packaging architectures relies on good adhesion of the solderable PVD film stack sputtered at the backside of the active Si chips. In addition to heat dissipation to the substrate, the coupling by thermal interface materials (TIMs) enables optimized heat management due to their material properties. The better the adhesion is between two layers, the more reliable is the heat dissipation. This is particularly important in heterogeneous integration (HI), where multiple chips with different functionality, size, thickness and planarity are integrated in the same package. This study characterizes the adhesion of seven different backside metallization (BSM) stacks deposited on test vehicles consisting of Si and epoxy mold compound (EMC). The stacks differ in terms of various wafer pre-treatment such as ICP sputter etching and different adhesion layers. Additionally, a moisture sensitivity level (MSL) test is carried out to investigate whether a combination of moisture and thermal expansion can provoke delamination between EMC and metallization. Overall, it can be shown with which BSM stack and under which pre-treatment the adhesion to Si and EMC can be improved.