A high-speed adaptive image DCT coder with parallel architecture for VLSI implementation

A new efficient discrete cosine transform (DCT) for bit rate reduction of video signals is presented. The design combines a parallel two-dimensional DCT architecture with distributed coder functions. By taking advantage of the symmetry in the DCT matrix, the internal clock rate is reduced to a factor of 4. This circuit is applicable in advanced television systems (HDTV) operating at video sampling rate up to 80 MHz and can be realized in CMOS technology as a single VLSI component. This architecture utilizes the advantage of parallel and distributed arithmetic to achieve high-speed performance.