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2024
Poster
Title
Implementing ALD in post-CMOS-compatible 200 mm wafer processes
Title Supplement
Poster presented at the 24th International Conference on Atomic Layer Deposition, 4-7 August 2024, Helsinki
Abstract
The successful implementation of new ALD materials in standard 200 mm wafer fabrication processes poses challenges, particularly concerning post-processing stability of (semi-)conductive materials. This study addresses the critical issue of ensuring the stability of thin layers during post-processing steps such as patterning, chemical etching, and resist removal. Since ALD as a process is primarily predestined for thin layers consisting of a few monolayers, the influence of further process steps must be evaluated all the more critically due to the high surface to layer thickness ratio. For instance, ion beam etching processes can lead to photoresist cross-linking, requiring plasma ashing of the resist. Additionally, chemical selective etching may result in underetching of the photoresist, leading to alterations in critical dimensions as well as typical cleaning processes may attack the sensitive layers. The specific focus of this work is on the post-processing of MoS2, a semi conductive material, deposited by ALD at low temperatures (T = 100 °C) for gas sensing applications. To assess its stability and suitability for industrial high-volume processes, the sheet resistance of the MoS2 layer is measured before and after typical post-processing steps. By analyzing the sheet resistance of the MoS2 layer, valuable insights can be gained regarding its stability against further processing steps in semiconductor manufacturing. These insights are crucial for assessing the feasibility of integrating MoS2 and similar ALD materials into industrial-scale processes
Author(s)
Rights
Under Copyright
Language
English
Keyword(s)