An integrated approach to utilize designer's debug capacity in system-on-a-chip designs

Modern integrated circuits and systems consist of many different functional blocks where the currently available chip capacity allows to integrate complete systems onto a single chip which is called System-on-a-Chip (SoC). The increasing design complexity and scale of SoC designs makes the verification of the functional correctness a complex and crucial task. One possible solution is a raising of the abstraction level towards the Electronic System Level (ESL). Creating correct and reliable system models is an essential requirement for successful ESL design. One key issue is to find as many errors as possible fast and early during development. The presented thesis proposes an integrated approach for a systematic verification at ESL. Four validation techniques accompany the development stages of a system model starting as soon as first blocks are available and continuing with subsystems until the entire model is completed. The techniques improve and accelerate error detection, observation, and isolation as well as design understanding. Hence, their continued application minimizes the number of errors that escape to the next development stage. All techniques have been prototypically implemented for SystemC and their efficiency is proven on real-world industrial designs.