An area-optimized serial implementation of ICEPOLE authenticated encryption schemes
Abstract
ICEPOLE is a high-speed, hardware-oriented family of authenticated encryption schemes aimed at high-throughput data processing. It is one of the candidates admitted to the second round of the ongoing CAESAR competition for selecting dedicated authenticated encryption schemes. One goal of the second round is the evaluation of hardware implementations. Although ICEPOLE is designed for high-speed applications, the evaluation of both parallel and serialized designs is necessary in order to have a fair comparison with other submitted candidates. In this work, we study and evaluate different hardware design architectures and their trade-offs for area and throughput. In particular, we focus on a compact 20-bit slice-based serial implementation of ICEPOLE. Our implementation is > 85% smaller than the state-of-art 1280-bit fully parallel implementation on low-end, high-end and low-power FPGAs (Xilinx Spartan 3E, Virtex-6 and Artix-7), yet retains considerably high-throughput.
