Fluorine contamination of PHEMTs during processing

The threshold voltage of PHEMTs fabricated by a selective dry etched gate recess using fluorine containing plasma, is higher than expected from calculations. An increase in dry etch time increases the threshold voltage. The recess depth is hardly effected by the etch time, because the dry etching stops on AlGaAs by forming non volatile ALE. We investigated MBE grown doped GaAs layers and HEMT structures after fluorine plasma treatment and different post dry etch dips. before and after annealing. A drastic increase in sheet resistance of these layers was observed. SIMS depth profiling identified fluorine at the surface, fluorine diffusion into silicon doped GaAs, fluorine accumulation at the GaAs/AlGaAs interface and at the silicon pulse doping. We conclude, that the observed positive shift in threshold voltage is due to compensation of silicon donors, acceptor states or electron traps caused by fluorine.