Assessing thermal resistance as a degradation metric for solder bump arrays in discrete SiC MOSFET packages

The development of innovative power electronics solutions for automotive applications introduces new reliability requirements for electronic assemblies and interconnection technologies. Many of the reliability methods used in power electronics require extensive experimental data, resulting in long product design cycles. This work focuses on developing a simulation-driven approach to assess the solder joint reliability of a discrete silicon carbide MOSFET by monitoring its degradation under power cycling in the thermal and thermo-mechanical domains using the thermal resistance of the stack as a failure metric. Active power cycling tests are performed to determine the loading condition at which end-of-life is reached due to a 20 % increase in thermal resistance. Numerical analysis using finite element simulations is conducted to gain a physical understanding of the failure criterion, allowing to monitor solder degradation based on the thermal resistance and to pinpoint failure at individual interconnects within a solder bump array. The proposed methodology aims to accelerate the quality assurance and product qualification processes of discrete power electronic devices.