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  4. Vertical interconnections using through encapsulant via (TEV) and through silicon via (TSV) for high-frequency system-in-package integration
 
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2014
Conference Paper
Title

Vertical interconnections using through encapsulant via (TEV) and through silicon via (TSV) for high-frequency system-in-package integration

Abstract
In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window.
Author(s)
Wojnowski, M.
Infineon Technologies AG Neubiberg Germany
Pressel, K.
Infineon Technologies AG Regensburg Germany
Beer, G.
Infineon Technologies AG Regensburg Germany
Heinig, Andy  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Dittrich, Michael
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Wolf, Jürgen
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Mainwork
IEEE 16th Electronics Packaging Technology Conference, EPTC 2014. Proceedings  
Conference
Electronics Packaging Technology Conference (EPTC) 2014  
Open Access
File(s)
Download (520.97 KB)
DOI
10.24406/publica-r-386582
10.1109/EPTC.2014.7028413
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
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