Bump arrays for RF applications modeling methodology

The advantages offered by area array packages over peripherally leaded packaging approaches were discussed. The advantages arises from the use of bump arrays for signal transmission from the chip to the package and the package to the board. The design requires accurate electrical models for bump arrays that account for their parasitic effects in the GHz range. It was shown that the electrical parameters extracted from a single bump and two-coupled bumps could be used to characterize any bump array.