UVM-SystemC based hardware in the loop simulations for accelerated Co-Verification

Stricter and higher safety requirements at a higher cost-efficiency together with the tremendous growth in the silicon integration capability in recent years have pushed automotive electronic systems to a safe system-on-chip architecture approach. This is especially true for a modern airbag system application, which is a safety critical heterogeneous mixed-signal real-time system. As a consequence, verification of those systems is becoming an increasingly time consuming and costly task, which cannot be handled by a classical simulation-based development flow anymore. System emulation, as well as hardware in the loop (HIL) techniques for system integration and test are widely used by Tier-1 and OEMs and more recently are also accepted by Tier-2 suppliers. Despite this, an in-efficiency on the link between simulation-based development and HIL/Emulation based development still exists, especially on the interchangeability of test descriptions between both steps. To overcome this we propose to run UVM-SystemC on HIL systems, allowing them to re-use the verification environment with its test benches. This re-use enables a tight relationship between the computer based verification and the HIL based lab validation and therefore helps to reduce the time of a redesign cycle. It also speeds up root cause analysis in the case of bug findings during the lab validation. To realize the proposed strategy, different established methods and techniques are combined, which will be illustrated within this paper on the basis of an industrial airbag system application.