BER optimization for micro power receivers using quick and accurate system simulation

The designer of practical receivers must deal with several problems in the analog as well as in the digital part. All these undesired effects have a large impact on the system performance, which is commonly described in terms of bit error rate (BER) or packed error rate (PER). In various textbooks, the theoretical relation between Eb/N0 and BER is only given for an assumed perfect receiver system. However, the theoretical equations are not capable to predict the performance of a system in presence of an interferer or non ideal components correctly. Instead, a system simulation is necessary. In this contribution, a model of the analog front-end (AFE) will be introduced, which describe several effects which can occur. This model can be used to determine and to verify specifications of the whole front-end or of its single stages. Simulation results are presented, which reveal that simple assumption made in common theory did not hold.