A verification methodology for programmable and reconfigurable processors

An innovative approach for functional verification, embedded in a design and verification environment, will be presented. The approach permints the reuse of test patterns by the combination of a top level test-bench and subordinated module test-benches in a unique manner. It is based on a new Add-on tool, which extends ModelSim/Questa by powerful features to stimulate, compare, and trace of signals. The tool is used for pattern transfer inside hierarchical test-benches, for automated evaluation of hundreds of thousands of patterns in regression test suites and for injection of test-pattern generated by third party tools. Furthermore, a use case of the tool for simulation of partial dynamic hardware reconfiguration is shown.