High speed interfaces between chips mounted with different integration technologies on an interposer

Continuous trend over the previous decades towards faster smaller systems was mainly driven by Moore's Law. Smaller transistors drove higher speeds and clocks making the systems faster and faster. But this trend has slowed down now due to further shortening of transistor channel lenght hitting a wall. This has led to investigation of out of the box integration technologies which can make use of smart techniques to put together already available fast component leading to an increased performance in power and area aspects. One such technology is 2.5D integration which connects multiple dies onto a passive interposer with dense interconnect capable metal layers. To investigate the performance of such a solution, this paper shows the 3D extracted complete channel model of 2.5D connected IOs. Then simulation results are shown using industry standard IBIS models to understand different IO interface circuitries' performance in 2.5D interconnect environment. Finally comparisons are made in terms of area, power and speed of different IO types to show which one is most suitable in a certain application.