Generierung von Verhaltensmodellen aus ANSYS-Beschreibungen
For the design of components of microsystems FEM-tools like ANSYS are successfully applied. On the other hand side the verification on system level with powerful circuit and system simulation engines like Eldo, Saber and VHDL-AMS simulators that are widely used in Microelectronics are also getting more and more accepted in the design process of microsystems. To exploit the advantages of system simulation appropriate behavioural models of the components are needed. The paper explains how such models implemented in different description languages (HDL-A, Mast, VHDL-AMS) can be derived using ANSYS substructuring facilities. The accuracy of the behavioural models depends on the number and position of terminal and additional internal nodes that are defined before the substructuring. An example demonstrates this dependency. The algorithm development is funded by the BMBF (Federal Ministry of Science, Education and Research) in the EKOSAS project (16SV1161).