Investigation of a rigid carrier CSP with the microDAC method

It has been shown that the warpage of the mounted CSP is reduced with increasing temperature. This is not surprising because the investigated CSP uses flip chip technology. The warpage is caused by the different CTE of Silicon and organic carrier during cooling down from the cure temperature of the underfill. The microDAC shows that the PCB is deflected nearly about the same amount without introducing a significant shear strain in the solder joints. Hence the warpage - at least in the measured range - will no not significantly influence the solder fatigue, which is caused by stress and strain in the solder joints.