1990
Conference Paper
Title

A 1.90 GBit/s monolithic comparator implemented on an analog bipolar array

Abstract
A monolithic comparator with sample rates up to 1.9 Bbit/s integrated on an analog array is presented. The circuit has been implemented on an analog array in a standard bipolar process (fT, NPN = 6.5 GHz). A parallel circuit structure doubles maximum sampling rate.
Author(s)
Cepl, F.
Sauerer, J.
Hagelauer, R.
Seitzer, D.
Mainwork
Conference
DOI
Language
English