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  4. 28nm HKMG 1F-1R2 Multilevel Memory for Inference Engine Application
 
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2023
Conference Paper
Title

28nm HKMG 1F-1R2 Multilevel Memory for Inference Engine Application

Abstract
This article reports 28 nm high-k-metal-gate (HKMG) based 3bits/cell memory with one ferroelectric (Fe) field effect transistor (FeFET) and one reconfigurable resistor (R2). R2, connected with the select line (SL) and the drain terminal of the FeFET, can be reconfigured via the SL terminal. R2 can be implemented by using a standard metal-oxide-semiconductor field effect transistor (MOSFET) as voltage controlled resistor or any two terminal programmable resistors. The detailed discussion about R2 is beyond the scope of this paper. The 1F-1R2 cells demonstrate current-based 3bits/cell operation over a 300mm wafer and stable retention characteristics at 85°C for all eight current levels.
Author(s)
De, Sourav
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Müller, Franz  
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Lederer, Maximilian
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Raffel, Yannick
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Ali, Tarek
Pirro, Luca
Dünkel, Stefan
Beyer, Sven
Seidel, Konrad  
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Kämpfe, Thomas  orcid-logo
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Mainwork
International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023. Proceedings of Technical Papers  
Conference
International VLSI Symposium on Technology, Systems and Applications 2023  
DOI
10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134004
Language
English
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
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